1. Field of the Invention
The present invention relates to complementary metal-oxide-semiconductor (CMOS) image sensors, and more particularly, to a CMOS image sensor and a method for manufacturing the same, in which a nitride layer for passivation is used as a microlens to reduce topology.
2. Discussion of the Related Art
FIGS. 1-6 respectively illustrate sequential process steps of a method for fabricating a CMOS image sensor according to a related art.
FIG. 1 illustrates a unit pixel region and a peripheral region of a pad, a P-well 50 and an N-well formed by selectively implanting boron ions into a silicon substrate. A field oxide layer 60 is formed by filling a trench using a device isolation process. A gate oxide layer (not shown) is then formed at a desired thickness according to a desired threshold voltage. A polysilicon layer 40 and a tungsten silicide layer 80 to be used as a gate electrode are formed on the gate oxide layer. Then, the polysilicon layer 40 and the tungsten silicide layer 80 are selectively etched to form the gate electrode of a device. Subsequently, an N-type ion-implantation region 20 and a P-type ion-implantation region 10 are formed in the silicon substrate by selective ion implantation to form a photodiode. The wells are lightly doped to form source and drain regions of a lightly doped drain structure. A tetra-ethyl-ortho-silicate oxide layer or a silicon nitride (SiN) layer is deposited by low-pressure chemical vapor deposition. The tetra-ethyl-ortho-silicate oxide layer or the silicon nitride layer is etched back to form a spacer 70 at sidewalls of the gate electrode. Then, an N-type junction region 30 and a P-type junction region are formed by heavily doping the silicon substrate to form source and drain regions.
As shown in FIG. 2, the tetra-ethyl-ortho-silicate oxide layer is to be used as a pre-metal dielectric (PMD) layer 90. The PMD layer 90 is formed to a thickness of 1,000 Å by low-pressure chemical vapor deposition. A borophosphate-silicate-glass layer is formed on the tetra-ethyl-ortho-silicate oxide layer by high-pressure chemical vapor deposition. The borophosphate-silicate-glass layer then undergoes a heating process for flowing. A predetermined junction region and a contact hole 100 that exposes the gate electrode are then formed by selectively etching the PMD layer 90. Subsequently, a titanium layer 110 serving as an adhesive layer, an aluminum layer 120 for interconnection, and a non-reflective titanium nitride (TiN) layer 130 are respectively deposited and selectively etched to form a first metal line. The contact hole 100 is formed by a plasma etching process.
As shown in FIG. 3, a tetra-ethyl-ortho-silicate oxide layer 150 and a spin-on-glass oxide layer 140 are formed by plasma-enhanced chemical vapor deposition. Then, the tetra-ethyl-ortho-silicate oxide layer 150 and the spin-on-glass oxide layer 140 undergo a heating process and planarization. Next, an oxide layer is deposited on the tetra-ethyl-ortho-silicate oxide layer 150 and the spin-on-glass oxide layer 140 by plasma-enhanced chemical vapor deposition to form a first IMD layer 160.
As shown in FIG. 4, a via hole is formed by selectively etching the first IMD layer 160. A titanium layer, the aluminum layer, and the titanium nitride layer are deposited and etched by the plasma etching process to form a second metal line. Subsequent formations of another tetra-ethyl-ortho-silicate oxide layer, another spin-on-glass oxide layer, and another oxide layer are formed in the same manner as the first IMD layer 90 to form a second PMD layer. The above steps are repeated according to the required number of metal line layers.
As shown in FIG. 5, after the uppermost metal line layer is formed, an oxide layer serving as a device passivation layer is deposited at a thickness of 8,000 Å by plasma-enhanced chemical vapor deposition. A metal layer around a pad area is exposed by a pad opening process so that the metal pad may be used as an electrode terminal. That is, the oxide layer for the device passivation layer and the titanium nitride layer are etched to form a pad opening.
As shown in FIG. 6, a color filter array layer 170 is formed. A planarization layer 180 is formed thereon. Then, a microlens layer 190 is formed on the planarization layer 180. That is, in a CMOS image sensor according to the related art as described above, the color filter array and microlens layers are formed after the formation of the oxide layer for passivation. However, this results in a topology of the manufactured device that is too great to obtain a high quality image.